https://github.com/JarryShaw/DigitLock-Verilog
基於FPGA板且使用Verilog語言編寫的電子密碼鎖程序
https://github.com/JarryShaw/DigitLock-Verilog
Last synced: 6 months ago
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基於FPGA板且使用Verilog語言編寫的電子密碼鎖程序
- Host: GitHub
- URL: https://github.com/JarryShaw/DigitLock-Verilog
- Owner: JarryShaw
- Archived: true
- Created: 2017-05-02T12:57:35.000Z (almost 8 years ago)
- Default Branch: master
- Last Pushed: 2017-11-27T15:26:45.000Z (over 7 years ago)
- Last Synced: 2024-05-22T19:32:04.747Z (11 months ago)
- Language: Verilog
- Homepage:
- Size: 606 KB
- Stars: 1
- Watchers: 3
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
Awesome Lists containing this project
- awesome-scs - 2017 - DigitLock-Verilog
README
# Digit Lock for FPGA
* Capable with ISE Design Suite.
* File DigitLock.v is the main code written in Verilog.
* Report of the experiment is attached also, as DigitLock.pdf.
* Folder DigitLocker holds the whole ISE project, but be aware that *.ucf might vary from the FPGA boards.