https://github.com/JarryShaw/Verilog

Verilog Assignment of DSD (SJTU)
https://github.com/JarryShaw/Verilog

Last synced: about 1 month ago
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Verilog Assignment of DSD (SJTU)

• Host: GitHub
• URL: https://github.com/JarryShaw/Verilog
• Owner: JarryShaw
• License: unlicense
• Archived: true
• Created: 2017-12-10T13:45:39.000Z (over 7 years ago)
• Default Branch: master
• Last Pushed: 2018-04-10T07:10:21.000Z (about 7 years ago)
• Last Synced: 2024-05-22T19:33:10.525Z (about 1 year ago)
• Language: Verilog
• Size: 15.7 MB
• Stars: 1
• Watchers: 3
• Forks: 4
• Open Issues: 0
• Metadata Files:
  • License: LICENSE

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• awesome-scs - 2017 - Verilog