https://github.com/Juniper/open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
https://github.com/Juniper/open-register-design-tool
asic eda fpga jspec register-descriptions registers systemrdl systemrdl-compiler systemverilog uvm
Last synced: 7 months ago
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Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
- Host: GitHub
- URL: https://github.com/Juniper/open-register-design-tool
- Owner: Juniper
- License: apache-2.0
- Created: 2016-06-14T18:33:32.000Z (over 9 years ago)
- Default Branch: master
- Last Pushed: 2024-10-21T20:31:57.000Z (about 1 year ago)
- Last Synced: 2025-05-06T19:10:16.904Z (8 months ago)
- Topics: asic, eda, fpga, jspec, register-descriptions, registers, systemrdl, systemrdl-compiler, systemverilog, uvm
- Language: Verilog
- Homepage:
- Size: 7.08 MB
- Stars: 199
- Watchers: 43
- Forks: 71
- Open Issues: 25
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Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
- awesome-opensource-hardware - open-register-design-tool
README
# open-register-design-tool
Ordt is a tool for automation of IC register definition and documentation. It currently supports 2 input formats:
1. SystemRDL - a stardard register description format released by [Accellera.org](http://accellera.org/activities/working-groups/systemrdl)
2. JSpec - a register description format used within Juniper Networks
The tool can generate several outputs from SystemRDL or JSpec, including:
- SystemVerilog/Verilog RTL code description of registers
- UVM model of the registers
- C++ and python models of the registers
- C header file providing register address and field defines
- XML and text file register descriptions
- SystemRDL and JSpec (conversion)
Easiest way to get started with ordt is to download a runnable jar from the [Juniper repo release area](https://github.com/Juniper/open-register-design-tool/releases).
Ordt documentation can be found [here](https://github.com/Juniper/open-register-design-tool/wiki).