https://github.com/Juniper/open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
https://github.com/Juniper/open-register-design-tool

asic eda fpga jspec register-descriptions registers systemrdl systemrdl-compiler systemverilog uvm

Last synced: 3 months ago
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Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

• Host: GitHub
• URL: https://github.com/Juniper/open-register-design-tool
• Owner: Juniper
• License: apache-2.0
• Created: 2016-06-14T18:33:32.000Z (over 8 years ago)
• Default Branch: master
• Last Pushed: 2023-07-28T18:36:45.000Z (over 1 year ago)
• Last Synced: 2024-07-15T13:53:36.976Z (4 months ago)
• Topics: asic, eda, fpga, jspec, register-descriptions, registers, systemrdl, systemrdl-compiler, systemverilog, uvm
• Language: Verilog
• Homepage:
• Size: 7.03 MB
• Stars: 184
• Watchers: 43
• Forks: 67
• Open Issues: 23
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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• awesome-opensource-hardware - open-register-design-tool

README

        
# open-register-design-tool

Ordt is a tool for automation of IC register definition and documentation.  It currently supports 2 input formats:

  1. SystemRDL - a stardard register description format released by [Accellera.org](http://accellera.org/activities/working-groups/systemrdl)

  2. JSpec - a register description format used within Juniper Networks

The tool can generate several outputs from SystemRDL or JSpec, including:

  - SystemVerilog/Verilog RTL code description of registers

  - UVM model of the registers

  - C++ and python models of the registers

  - C header file providing register address and field defines

  - XML and text file register descriptions

  - SystemRDL and JSpec (conversion)

Easiest way to get started with ordt is to download a runnable jar from the [Juniper repo release area](https://github.com/Juniper/open-register-design-tool/releases).

Ordt documentation can be found [here](https://github.com/Juniper/open-register-design-tool/wiki).