https://github.com/Nic30/hdlConvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
https://github.com/Nic30/hdlConvertor

antrl4 fpga parser python systemverilog systemverilog-parser verilog verilog-parser vhdl vhdl-parser

Last synced: 3 months ago
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Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

• Host: GitHub
• URL: https://github.com/Nic30/hdlConvertor
• Owner: Nic30
• License: mit
• Created: 2016-06-28T13:19:49.000Z (over 8 years ago)
• Default Branch: master
• Last Pushed: 2024-09-03T22:12:39.000Z (4 months ago)
• Last Synced: 2024-10-25T00:19:52.745Z (3 months ago)
• Topics: antrl4, fpga, parser, python, systemverilog, systemverilog-parser, verilog, verilog-parser, vhdl, vhdl-parser
• Language: C++
• Homepage:
• Size: 14.5 MB
• Stars: 281
• Watchers: 22
• Forks: 66
• Open Issues: 34
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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