https://github.com/Nic30/hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++
https://github.com/Nic30/hwt

codegen codegenerator compiler fpga hcl hls rtl simulator systemc systemverilog uvm verilog vhdl

Last synced: about 1 month ago
JSON representation

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

• Host: GitHub
• URL: https://github.com/Nic30/hwt
• Owner: Nic30
• License: mit
• Created: 2015-05-19T17:45:47.000Z (almost 10 years ago)
• Default Branch: master
• Last Pushed: 2024-11-23T16:25:41.000Z (5 months ago)
• Last Synced: 2025-03-11T04:11:23.747Z (about 1 month ago)
• Topics: codegen, codegenerator, compiler, fpga, hcl, hls, rtl, simulator, systemc, systemverilog, uvm, verilog, vhdl
• Language: Python
• Homepage:
• Size: 19.1 MB
• Stars: 207
• Watchers: 17
• Forks: 28
• Open Issues: 11
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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