https://github.com/Nic30/hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++
https://github.com/Nic30/hwt

codegen codegenerator compiler fpga hcl hls rtl simulator systemc systemverilog uvm verilog vhdl

Last synced: about 2 months ago
JSON representation

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

• Host: GitHub
• URL: https://github.com/Nic30/hwt
• Owner: Nic30
• License: mit
• Created: 2015-05-19T17:45:47.000Z (over 9 years ago)
• Default Branch: master
• Last Pushed: 2024-10-23T18:29:10.000Z (2 months ago)
• Last Synced: 2024-10-24T04:03:34.048Z (2 months ago)
• Topics: codegen, codegenerator, compiler, fpga, hcl, hls, rtl, simulator, systemc, systemverilog, uvm, verilog, vhdl
• Language: Python
• Homepage:
• Size: 19 MB
• Stars: 202
• Watchers: 18
• Forks: 27
• Open Issues: 10
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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