https://github.com/OpenTimer/OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems
https://github.com/OpenTimer/OpenTimer

cad circuit-analysis circuit-simulation circuit-simulator computer-aided-design cpp17 eda electronic-design-automation parallel-computing sta static-timing-analysis verilog vlsi vlsi-circuits vlsi-physical-design

Last synced: about 2 months ago
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A High-performance Timing Analysis Tool for VLSI Systems

• Host: GitHub
• URL: https://github.com/OpenTimer/OpenTimer
• Owner: OpenTimer
• License: other
• Created: 2015-07-14T14:26:43.000Z (over 9 years ago)
• Default Branch: master
• Last Pushed: 2023-05-26T02:32:37.000Z (over 1 year ago)
• Last Synced: 2024-07-31T19:17:03.963Z (4 months ago)
• Topics: cad, circuit-analysis, circuit-simulation, circuit-simulator, computer-aided-design, cpp17, eda, electronic-design-automation, parallel-computing, sta, static-timing-analysis, verilog, vlsi, vlsi-circuits, vlsi-physical-design
• Language: Verilog
• Homepage:
• Size: 329 MB
• Stars: 538
• Watchers: 47
• Forks: 146
• Open Issues: 56
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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