https://github.com/PyHDI/veriloggen

Veriloggen: A Mixed-Paradigm Hardware Construction Framework
https://github.com/PyHDI/veriloggen

compiler hardware hardware-construction-language high-level-synthesis python pyverilog verilog-hdl

Last synced: 13 days ago
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Veriloggen: A Mixed-Paradigm Hardware Construction Framework

• Host: GitHub
• URL: https://github.com/PyHDI/veriloggen
• Owner: PyHDI
• License: apache-2.0
• Created: 2015-06-21T15:05:30.000Z (over 9 years ago)
• Default Branch: develop
• Last Pushed: 2024-08-10T03:27:48.000Z (3 months ago)
• Last Synced: 2024-10-01T10:36:46.523Z (about 1 month ago)
• Topics: compiler, hardware, hardware-construction-language, high-level-synthesis, python, pyverilog, verilog-hdl
• Language: Python
• Homepage:
• Size: 11.4 MB
• Stars: 306
• Watchers: 35
• Forks: 58
• Open Issues: 23
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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