https://github.com/Shehab-Naga/ddr5_phy
DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
https://github.com/Shehab-Naga/ddr5_phy
gp systemverilog uvm
Last synced: 5 months ago
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DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
- Host: GitHub
- URL: https://github.com/Shehab-Naga/ddr5_phy
- Owner: Shehab-Naga
- License: mit
- Created: 2022-06-30T11:56:20.000Z (over 3 years ago)
- Default Branch: main
- Last Pushed: 2024-03-21T06:13:07.000Z (over 1 year ago)
- Last Synced: 2024-11-17T09:39:50.620Z (11 months ago)
- Topics: gp, systemverilog, uvm
- Language: SystemVerilog
- Homepage:
- Size: 13 MB
- Stars: 42
- Watchers: 2
- Forks: 22
- Open Issues: 1
-
Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
- awesome-opensource-hardware - ddr5_phy
README
# DDR5 PHY Verification
This repo includes the uvm testbench for DDR5 PHY as part of Graduation project titled "Verification of the Digital Data-Path of DDR5 PHY" in Nanotechnology & Nano-Electronics Engineering program - Zewail City (2021 - 2022)
***************************************************************************
Files Organization:
- docs: Thesis, Verification plan & Waveforms for illustration
- rtl: The rtl is not included in this project as it is not part of this work
- scripts: Shell script for test run automation
- testbench: UVM tb environment (comps, sequences, tests, interfaces, transactions)
******************************************************************************
Brief Description:
A physical layer facilitates the communication between the memory controller and the DRAM. In order to perform this functionality, it should satisfy both communication protocols between the memory controller and PHY and between PHY and DRAM which are DDR PHY Interface (DFI 5.1) standard and JEDEC JESD209-5A standard respectively. Therefore, both standards are considered the golden references from which the PHY features and virtual environment will be constructed. Furthermore, the
project utilizes simulation-based verification using UVM and SystemVerilog. Hence, the testbench development will rely on the IEEE standards of UVM
and SystemVerilog too.
********************************************************************************
Team:
[Abdullah Allam](https://www.linkedin.com/in/abdullah-shaaban-154581167/),
[Shehab Naga](https://www.linkedin.com/in/shehabbahaaengineer/),
[Mohamed Abdelall](https://www.linkedin.com/in/mohamedabdelall/),
[John Aziz](https://www.linkedin.com/in/john-aziz-2824a9168/),
[Tarek Abou-Elkheir](https://www.linkedin.com/in/tarek-abdelnasser-b0aa27173/)