https://github.com/Shehab-Naga/ddr5_phy

DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
https://github.com/Shehab-Naga/ddr5_phy

gp systemverilog uvm

Last synced: about 2 months ago
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DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision

• Host: GitHub
• URL: https://github.com/Shehab-Naga/ddr5_phy
• Owner: Shehab-Naga
• License: mit
• Created: 2022-06-30T11:56:20.000Z (over 2 years ago)
• Default Branch: main
• Last Pushed: 2024-03-21T06:13:07.000Z (10 months ago)
• Last Synced: 2024-08-03T17:11:09.850Z (5 months ago)
• Topics: gp, systemverilog, uvm
• Language: SystemVerilog
• Homepage:
• Size: 13 MB
• Stars: 41
• Watchers: 2
• Forks: 19
• Open Issues: 1
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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