https://github.com/StanfordAHA/lake

Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory macros.
https://github.com/StanfordAHA/lake

Last synced: 2 months ago
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Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory macros.

• Host: GitHub
• URL: https://github.com/StanfordAHA/lake
• Owner: StanfordAHA
• License: bsd-3-clause
• Created: 2019-07-31T05:45:32.000Z (over 5 years ago)
• Default Branch: master
• Last Pushed: 2024-10-31T21:11:12.000Z (2 months ago)
• Last Synced: 2024-10-31T21:22:24.760Z (2 months ago)
• Language: Python
• Size: 5.02 MB
• Stars: 18
• Watchers: 20
• Forks: 2
• Open Issues: 13
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

• awesome-opensource-hardware - lake

README

        
# Lake: An Agile Framework for Designing and Automatically Configuring Physical Unified Buffers

Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory macros. Lake also comprises a library of generalized hardware modules aimed at memory controller designs.

## Install

`git clone github.com/StanfordAHA/lake`

`cd lake && pip install -e .`

## Run a test

To run a test, you can simply generate the verilog and push through your favorite verilog simulator. Alternatively, Lake uses the pytest framework for unit tests of constituent modules. These tests leverage [fault](https://github.com/leonardt/fault) and [verilator](https://www.veripool.org/wiki/verilator) for open source simulation. Tests should run and pass on Linux and MacOS.

## Documentation

Check out the [wiki](https://github.com/StanfordAHA/lake/wiki) of this github repo.