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https://github.com/SymbioticEDA/riscv-formal
RISC-V Formal Verification Framework
https://github.com/SymbioticEDA/riscv-formal
Last synced: about 1 month ago
JSON representation
RISC-V Formal Verification Framework
- Host: GitHub
- URL: https://github.com/SymbioticEDA/riscv-formal
- Owner: SymbioticEDA
- License: isc
- Created: 2016-11-28T17:47:50.000Z (about 8 years ago)
- Default Branch: master
- Last Pushed: 2022-04-06T01:24:21.000Z (over 2 years ago)
- Last Synced: 2024-08-02T01:33:32.735Z (4 months ago)
- Language: Verilog
- Size: 728 KB
- Stars: 570
- Watchers: 39
- Forks: 95
- Open Issues: 24
Awesome Lists containing this project
- awesome-formal-verification - riscv-formal - A re-usable formal verification framework for RISC-V CPU designs. (Hardware verification / Tools)
- awesome-formal-verification - riscv-formal - A re-usable formal verification framework for RISC-V CPU designs. (Hardware verification / Tools)