https://github.com/TerosTechnology/vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
https://github.com/TerosTechnology/vscode-terosHDL

fpga systemverilog verilog vhdl

Last synced: 3 months ago
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VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

• Host: GitHub
• URL: https://github.com/TerosTechnology/vscode-terosHDL
• Owner: TerosTechnology
• Created: 2020-05-13T22:12:52.000Z (over 4 years ago)
• Default Branch: dev
• Last Pushed: 2024-04-13T09:32:35.000Z (7 months ago)
• Last Synced: 2024-04-13T21:09:29.495Z (7 months ago)
• Topics: fpga, systemverilog, verilog, vhdl
• Language: JavaScript
• Homepage: https://terostechnology.github.io/terosHDLdoc/
• Size: 91.5 MB
• Stars: 486
• Watchers: 21
• Forks: 39
• Open Issues: 164
• Metadata Files:
  • Readme: README.md

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