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https://github.com/TomasBeranek/but-inc-project
Access Terminal in VHDL
https://github.com/TomasBeranek/but-inc-project
but-fit fit fitkit fitkit2 fpga fsm inc inc-project vhdl vut vut-fit
Last synced: 3 months ago
JSON representation
Access Terminal in VHDL
- Host: GitHub
- URL: https://github.com/TomasBeranek/but-inc-project
- Owner: TomasBeranek
- License: mit
- Created: 2022-01-27T22:01:50.000Z (almost 3 years ago)
- Default Branch: main
- Last Pushed: 2022-09-27T07:23:29.000Z (over 2 years ago)
- Last Synced: 2023-05-14T19:25:33.155Z (over 1 year ago)
- Topics: but-fit, fit, fitkit, fitkit2, fpga, fsm, inc, inc-project, vhdl, vut, vut-fit
- Language: VHDL
- Homepage:
- Size: 71.3 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0