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https://github.com/VHDL/awesome-vhdl

A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
https://github.com/VHDL/awesome-vhdl

List: awesome-vhdl

awesome collection vhdl vhdl-collection vhdl-ip-core vhdl-library

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A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.

Awesome Lists containing this project

README

        

[![CC0 - Public Domain](https://img.shields.io/github/license/vhdl/awesome-vhdl.svg)](https://github.com/VHDL/awesome-vhdl/blob/master/LICENSE.md)
[![Awesome](https://awesome.re/badge.svg)](https://awesome.re)

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# Awesome VHDL

A curated list of awesome VHDL IP cores, frameworks, libraries, software and related resources.

**Table of content:**

- [Libraries](#libraries)
- [IP Core Libraries](#ip-core-libraries)
- [IP Core Collections](#ip-core-collections)
- [IP Cores](#ip-cores)
- [Frameworks](#frameworks)
- [Verification Frameworks](#verification-frameworks)
- [Verification Models](#verification-models)
- [Memory Models](#memory-models)
- [Interface Models](#interface-models)
- [Tools](#tools)
- [Grammars](#grammers)
- [Parsers](#parsers)
- [Simulators](#simulators)
- [Package Managers](#package-managers)
- [Services](#services)
- [Code Quality](#code-quality)
- [Continuous Integration](#continuous-integration)
- [Continuous Documentation](#continuous-documentation)
- [Resources](#resources)
- [Books](#books)
- [Podcasts](#podcasts)
- [Twitter](#twitter)
- [Websites](#websites)
- [Weekly](#weekly)
- [Other Awesome Lists](#other-awesome-lists)
- [Contributing](#contributing)

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# Libraries

## IP Core Libraries

*Libraries containing multiple IP cores.*

* [The PoC-Library](https://github.com/VLSI-EDA/PoC) - A library of free, open-source and platform independent IP cores.

## IP Core Collections

*Collections containing multiple IP cores.*

# IP Cores

*Single IP cores.*

# Frameworks

## Verification Frameworks

*Frameworks for Verification.*

* [Open Source VHDL Verification Methodology (OSVVM)](https://github.com/OSVVM/OSVVM)
* [Universal VHDL Verification Methodology (UVVM)](https://github.com/UVVM/UVVM)

# Verification Models

*Single verification models.*

## Memory Models

*Verification Model for Memories*

## Interface Models

*Verification Model for Interfaces.*

# Tools

## Grammars

## Parsers

## Simulators

* [GHDL](https://github.com/ghdl/ghdl) - A free and open source VHDL simulator supporting VHDL-87/93/2002/2008.

## Package Managers

# Services

## Code Quality

## Continuous Integration

## Continuous Documentation

# Resources

## Books

## Twitter

## Websites

## Weekly

# Other Awesome Lists

*List of lists.*

* [awesome](https://github.com/sindresorhus/awesome)
* [awesome-hdl](https://github.com/drom/awesome-hdl)

# Contributing

Your contributions are always welcome! Please take a look at the [contribution guidelines](https://github.com/vhdl/awesome-vhdl/blob/master/CONTRIBUTING.md) first.

I will keep some pull requests open if I'm not sure whether those libraries are
awesome, you could [vote for them](https://github.com/vhdl/awesome-vhdl/pulls)
by adding :+1: to them. Pull requests will be merged when their votes reach **10**.

# License

[Creative Commons](https://creativecommons.org/) - [CC0 1.0 Universal (CC0 1.0)](https://creativecommons.org/publicdomain/zero/1.0/deed)

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If you have any question about this opinionated list, do not hesitate to contact
me [@PaebbelsLemmi](https://twitter.com/PaebbelsLemmi) on Twitter or open an [issue](https://github.com/VHDL/awesome-vhdl/issues/new)
on GitHub.