https://github.com/VUnit/vunit

VUnit is a unit testing framework for VHDL/SystemVerilog
https://github.com/VUnit/vunit

asic fpga systemverilog-hdl testbench unit-testing universal-verification-methodology verification verilog-hdl vhdl

Last synced: about 2 months ago
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VUnit is a unit testing framework for VHDL/SystemVerilog

• Host: GitHub
• URL: https://github.com/VUnit/vunit
• Owner: VUnit
• License: other
• Created: 2014-11-18T20:50:51.000Z (about 10 years ago)
• Default Branch: master
• Last Pushed: 2024-11-04T13:14:54.000Z (about 2 months ago)
• Last Synced: 2024-11-04T13:32:29.353Z (about 2 months ago)
• Topics: asic, fpga, systemverilog-hdl, testbench, unit-testing, universal-verification-methodology, verification, verilog-hdl, vhdl
• Language: VHDL
• Homepage: http://vunit.github.io/
• Size: 14.7 MB
• Stars: 735
• Watchers: 51
• Forks: 263
• Open Issues: 245
• Metadata Files:
  • Readme: README.md
  • Contributing: docs/contributing.rst
  • License: LICENSE.rst

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README

        


  

  

  

  





  





  

  

  

  

  



**VUnit** is an [open source](LICENSE.rst) unit testing framework for VHDL/SystemVerilog. It features the functionality

needed to realize continuous and automated testing of your HDL code. VUnit doesn't replace but rather complements

traditional testing methodologies by supporting a *test early and often* approach through automation.

**Read more** [about VUnit](http://vunit.github.io/about.html).

Contributing in the form of code, docs, feedback, ideas or bug reports is welcome.

Read our [contributing guide](https://vunit.github.io/contributing.html) to get started.