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https://github.com/Vlsir/Vlsir
Interchange formats for chip design.
https://github.com/Vlsir/Vlsir
Last synced: 3 months ago
JSON representation
Interchange formats for chip design.
- Host: GitHub
- URL: https://github.com/Vlsir/Vlsir
- Owner: Vlsir
- License: bsd-3-clause
- Created: 2021-12-17T01:44:31.000Z (about 3 years ago)
- Default Branch: main
- Last Pushed: 2024-04-26T16:34:37.000Z (9 months ago)
- Last Synced: 2024-04-26T23:45:50.391Z (9 months ago)
- Language: Python
- Size: 1.76 MB
- Stars: 22
- Watchers: 3
- Forks: 8
- Open Issues: 25
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Metadata Files:
- Readme: readme.md
- License: LICENSE
Awesome Lists containing this project
- awesome-hdl - VLSIR - IC Interchange Formats, defined in Google Protobuf SDL (Hardware Intermediate Representations)
- awesome-opensource-hardware - vlsir