https://github.com/WilsonChen003/HDLGen

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
https://github.com/WilsonChen003/HDLGen

asic automation hdl perl python rtl script soc verilog

Last synced: about 2 months ago
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HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

• Host: GitHub
• URL: https://github.com/WilsonChen003/HDLGen
• Owner: WilsonChen003
• Created: 2022-10-30T13:51:09.000Z (almost 2 years ago)
• Default Branch: master
• Last Pushed: 2023-10-31T10:55:00.000Z (11 months ago)
• Last Synced: 2024-04-17T07:06:07.299Z (5 months ago)
• Topics: asic, automation, hdl, perl, python, rtl, script, soc, verilog
• Language: Verilog
• Homepage:
• Size: 21.1 MB
• Stars: 75
• Watchers: 7
• Forks: 20
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • Changelog: Change_History

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• awesome-hdl - HDLGen - Tool for processing of embedded Perl or Python scripts in Verilog source code. (Other Design Automation tools)