https://github.com/YangLeiSX/DigitalSystemDesignSJTU

code for course IS208 (Digital System Design) in SJTU
https://github.com/YangLeiSX/DigitalSystemDesignSJTU

Last synced: 3 months ago
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code for course IS208 (Digital System Design) in SJTU

• Host: GitHub
• URL: https://github.com/YangLeiSX/DigitalSystemDesignSJTU
• Owner: YangLeiSX
• Created: 2019-11-24T12:22:57.000Z (about 5 years ago)
• Default Branch: master
• Last Pushed: 2020-06-17T09:43:07.000Z (over 4 years ago)
• Last Synced: 2024-05-22T19:33:20.426Z (9 months ago)
• Language: Verilog
• Size: 66.4 KB
• Stars: 1
• Watchers: 0
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

Awesome Lists containing this project

• awesome-scs - 2019 - DigidalSystemDesignSJTU

README

        
# DigitalSystemDesignSJTU

上海交通大学

数字系统设计课程 Verilog HDL设计电路 

包括平时课程训练的组合逻辑电路，时序逻辑电路和大作业的题目代码

以及RISC架构的CPU设计并计算斐波那契数列的实现