https://github.com/ZipCPU/openarty

An Open Source configuration of the Arty platform
https://github.com/ZipCPU/openarty

arty fpga fpga-soc verilator wishbone wishbone-bus zipcpu

Last synced: 3 months ago
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An Open Source configuration of the Arty platform

• Host: GitHub
• URL: https://github.com/ZipCPU/openarty
• Owner: ZipCPU
• Created: 2016-09-26T16:21:53.000Z (over 8 years ago)
• Default Branch: master
• Last Pushed: 2024-01-17T00:20:03.000Z (about 1 year ago)
• Last Synced: 2024-08-08T13:15:18.095Z (7 months ago)
• Topics: arty, fpga, fpga-soc, verilator, wishbone, wishbone-bus, zipcpu
• Language: Verilog
• Size: 14.2 MB
• Stars: 118
• Watchers: 14
• Forks: 24
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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