https://github.com/a-bdellatif/frequencydivider

verilog code for frequency divider circuit implemented with verilog hdl
https://github.com/a-bdellatif/frequencydivider

digital-design fpga frequency-divider hardware-description-language hdl verilog

Last synced: about 2 hours ago
JSON representation

verilog code for frequency divider circuit implemented with verilog hdl

• Host: GitHub
• URL: https://github.com/a-bdellatif/frequencydivider
• Owner: a-bdellatif
• License: mit
• Created: 2024-12-03T15:41:38.000Z (2 months ago)
• Default Branch: main
• Last Pushed: 2025-01-21T10:44:31.000Z (13 days ago)
• Last Synced: 2025-01-25T10:27:50.925Z (9 days ago)
• Topics: digital-design, fpga, frequency-divider, hardware-description-language, hdl, verilog
• Language: Verilog
• Homepage:
• Size: 7.81 KB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

README

        
#### Frequency divider with verilog : 

frequency divider circuit that outputs three different clocks with(50 Khz, 100 Khz and 250 Khz).

* Clock 1 : 250 Khz

* Clock 2 : 100 Khz

* Clock 3 : 50 Khz

the verilog code was tested in ModelSim using ModelSim simulator, you can check the simulation by reviewing the [@simulation](https://github.com/0xaB26/FrequencyDivider/blob/main/wave)