https://github.com/aaronc81/stack-processor
WIP stack processor in Verilog for TinyFPGA BX
https://github.com/aaronc81/stack-processor
Last synced: 10 months ago
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WIP stack processor in Verilog for TinyFPGA BX
- Host: GitHub
- URL: https://github.com/aaronc81/stack-processor
- Owner: AaronC81
- Created: 2023-05-06T21:41:43.000Z (over 2 years ago)
- Default Branch: main
- Last Pushed: 2023-05-06T23:55:18.000Z (over 2 years ago)
- Last Synced: 2025-03-06T15:17:08.840Z (10 months ago)
- Language: Verilog
- Size: 16.6 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
Awesome Lists containing this project
README
A work-in-progress stack processor implemented in Verilog, targeting the TinyFPGA BX.
## Build
As committed, one module is missing, `instruction_memory`, which may be generated by assembling a
program using the `assemble.rb` script.
The `go` script will assemble, build, and upload for you:
```
$ ./go programs/add.asm
yosys -p "synth_ice40 -json hardware.json" -q block_mem.v instruction_memory.v top.v
...
TinyProg CLI
------------
Using device id 1d50:6130
...
```
## Test
There's a test suite bodged together with the `test.rb` Ruby script, which looks for special
assertion markers within the assembly code in `programs`.
```
$ ruby test.rb
Discovered 2 tests:
- add (2 assertions)
- simple_push_inc (2 assertions)
=== Running: add ===
Assemble | Simulate | Load | Check
top == 9
count == 1
PASSED
=== Running: simple_push_inc ===
Assemble | Simulate | Load | Check
top == 8
count == 1
PASSED
```