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https://github.com/abdallahabusedo/cmp305-introduction-verilog
introduction to Verilog in Integrated Circuit Design And VLSI technology
https://github.com/abdallahabusedo/cmp305-introduction-verilog
verilog verilog-code verilog-hdl verilog-project
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introduction to Verilog in Integrated Circuit Design And VLSI technology
- Host: GitHub
- URL: https://github.com/abdallahabusedo/cmp305-introduction-verilog
- Owner: abdallahabusedo
- Created: 2021-04-08T19:06:40.000Z (over 3 years ago)
- Default Branch: main
- Last Pushed: 2021-04-09T00:02:33.000Z (over 3 years ago)
- Last Synced: 2024-10-11T06:06:50.681Z (27 days ago)
- Topics: verilog, verilog-code, verilog-hdl, verilog-project
- Language: Verilog
- Homepage:
- Size: 5.86 KB
- Stars: 1
- Watchers: 2
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
# CMP305-introduction-Verilog
introduction to Verilog in Integrated Circuit Design And VLSI technology
# THIS IS A NOTES FOR MYSELF TAKEN FROM THIS VIDEO [LINK_OF_THE_VIDEO](https://www.youtube.com/watch?v=PJGvZSlsLKs)
# Verilog language
- Standard Hardware description Language (HDL).
- used to describe a digital system.
## Behavior Modeling
- A Component is described by its I/O response.
- only the functionality of the circuit no structure.
## Structural Modeling
- A component is described by interconnecting Lower-Level Component/primitives
- Both Functionality and structure of the circuit
## Register Transfer Level (RTL)
- A type of behavioral modeling for the purpose of synthesis
### Synthesis : Translating HDL to a circuit and then optimizing the represented circuit
# Module declaration
1) begins with keyword module
2) provides module name
3) include port list
```
module multi (
// port_list types
1- input => input port
2- output => output port
3- inout => bidirectional port
);
// port declaration
" ;"
// data type declatation
=> Net Data type
-> represents physical interconnect between structures
-- wire
-- tri
-- supply0
supply1
example
wire [7:0] out;
tri enable;
=> Variable Data type
-> represent element to store data temporarily
-- reg
-- integer
-- real
-- time
-- realtimer
// instantiation format
# (port_list);
# -> delay through component
// circuit functionality
// timing specifications
endmodule //multi
```
# Connecting Module Instantiation Ports
#### Two Methods to define ports connections
## 1) By Ordered list
- port connections defined by the order of the port list in the lower-level module declaration
```
module half_adder ( co , sum , a , b );
```
```
half_adder u1 ( c1 , s1 , a , b );
```
- the order dose matter
co -> c1 | sum -> S1 | a -> a | b -> b
## 2) By Name *(RECOMMENDED METHOD)*
- Port connections defined by name
- order does not matter
# Parameters
- Value assigned to a symbolic name
- must resolve to a constant at compile time
- can be overwritten at compile time
- "localparam" -> same as parameters but cannot be overwritten
ex
```
parameters size = 8; // can be overwritten
localparam outsize = 16; //can't be overwritten
```
# Numbers
1) Sized -> 3'b010 = 3bits wide binary number
- 3 indicated the size of number
2) Unsized -> 123 = 32bit decimal number
### Base Formats
- Decimal (d || D ) => 16'd255
- Hexadecimal (h || H) => 8'h9a
- Binary (b || B) => b1010
- Octal (o || O) => o21
- Signed (s || S) 16'shFA
### Negative numbers
- legal ==> -8'd3
- illegal ==> 4'd-2 ERROR
### Special Number Characters
- underlined ( _ ) used for readability
- 32'h21_65_bc_fe
- X or x unknown value
- 12'h12x
- z or Z high impedance value
- 1'bz
# Arithmetic operators
ain =5 ; bin =10 ; cin =2'b01; din =2'b0z
1) "+" => Add | bin+cin => 11
2) "-" => Subtract | bin-cin => 9
3) "*" => Multiply | ain*bin => 50
4) "/" => Divide | bin/ain => 2
5) "%" => Modulus | bin%ain => 0
6) "**"=> Exponent | ain**2 => 25
# Bitwise operators
1) "~" => | invert each bit
2) "&" => | And
3) "|" => | OR
4) "^" => | XOR
5) "^~" => | XNOR
# Reduction operators
1) "&" => | AND
2) "~&" => | NAND
3) "|" => | OR
4) "~|" => | NOR
5) "^" => | XOR
6) "~^" or "^~" => | XNOR
# Relational operators
1) ">" => | Grater than
2) "<" => | Less than
3) ">=" => | Greater than or equal
4) "<=" => | Less than or equal
# Equality operators
1) "==" => | Equality
2) "!=" => | inEquality
3) "===" => | Case Equality
4) "!==" => | Case inEquality
# Logical operators
1) "!" => | Not
2) "&&" => | AND
3) "||" => | OR
# Shift operators
1) "<<" => | logical shift left
2) ">>" => | logical shift right
3) "<<<" => | Arithmetic shift left
3) ">>>" => | Arithmetic shift right
# Miscellaneous operators
1) "?:" => | Conditional test
2) "{}" => | Concatenate
3) "{{}}" => | Replicate
# Making Assignments
## 1) Continuous Assignment Statement
```
wire[15:0] adder_out =mult_out + out;
```
equivalent to
```
wire[15:0] adder_out;
assign adder_out = mult_out + out;
```
when the RHS changes , expression is evaluated and LHS net is updated immediately.
## 2) Procedural Assignment Blocks
* Initial => used to initialized behavioral statements for simulation
* start at time 0
* execute only once during simulation then does not execute again
* statements inside execute sequentially
* Keywords begin and end must be used if block contains more than one statement
* Examples
* Initialization
* Monitoring
* any functionality that needs to be turned on just once
* Always => used to describe te circuit functionality using behavioral statements
* Blocks execute concurrently
* start at time 0
* and continuously in a looping fashion
* Behavioral statements inside an initial block execute sequentially
* Examples
* Modeling a digital circuit
* any Process or functionality needs to be executed continuously
- each one represent a separate process
- each consists of behavioral statements
Example on Always and initial statements
```
module clk_gen
#(parameters period =50)
(
output reg clk
);
initial clk = 1'b0;
always
#(period/2)clk =~clk;
initial #100 $finish;
endmodule
```
## Two Types of Procedural Assignments
1) Blocking Assignments =
- executed in the order they are specified in the seq. way
Example a=1 b=2
```
initial
begin
a = #5 b ;
c = #10 a;
end
```
|
| a=b=2 c=a=2
|_____|_____|_____|_____|_
0 5 10 15 20
2) Nonblocking Assignments <=
- allow scheduling of assignments without blocking execution of the statements that follow in a seq block
Example a=1 b=2
```
initial
begin
a <= #5 b ;
c <= #10 a;
end
```
|
| a=b=2 c=a=1
|_____|_____|_____|_____|_
0 5 10 15 20
- = for combinatorial logic
- <= for sequential logic
# Tow types of RTL processes
1) Combinatorial Processes
- sensitive to all inputs used in the Combinatorial logic
```
always @(a,b,sel)
always @*
```
2) Clocked Processes
- sensitive to clock or/and control signals
```
always @(Posedge clk , negedge clr_n)
```
# Behavioral Statements
1) if-else
```
always @* begin
if(s)
q=a;
else if(sb)
q=b;
else
q=c;
end
```
2) case
```
always @* begin
case(s)
2'b00 : q = a;
2'b01 : q = b;
2'b10 : q = c;
default : q =d;
endcase
end
```
3) Loop
- forever loop
```
initial begin
clk=0
forever #25 clk =~clk;
end
```
- repeat loopp
```
if(rotate ==1)
repeat (8) begin
tmp= data[15];
data={data<< 1 ,tmp};
end
```
- while loop
```
initial begin
count =0;
while (count < 101) begin
count = count+1;
end
end
```
- for loop
```
integer i;
always @(inp, cnt) begin
result[7:4]=0;
result[3:0]=inp;
if(cnt==1) begin
for(i=4; i<= 7 ; i=i+1) begin
result[i]=result[i-4];
end
result[3:0]=0;
end
end
```
# Function and Tasks
1) Function
- return one value
- produces combinatorial logic
- used in expressions
```assign mult_out = mult(ina,inb); ```
2) Tasks
- can return multi values
- can be combinatorial or registered
- task are invoked as statement
```stm_out(nxt,first,sel,filter); ```
there are more some differences between Function and Task
go and watch the video for more info and examples
thanks for reading
you are legend 😎