https://github.com/abdallahabusedo/combinational-multiplier

https://github.com/abdallahabusedo/combinational-multiplier

Last synced: 14 days ago
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• Host: GitHub
• URL: https://github.com/abdallahabusedo/combinational-multiplier
• Owner: abdallahabusedo
• Created: 2021-04-09T11:37:17.000Z (over 3 years ago)
• Default Branch: master
• Last Pushed: 2021-04-10T12:57:25.000Z (over 3 years ago)
• Last Synced: 2024-10-11T06:06:53.385Z (27 days ago)
• Language: Verilog
• Size: 367 KB
• Stars: 0
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: readme.md

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README

        


#  Design of Combinational Multiplier



#### - RTL implementation of a 4x4 multiplier for unsigned numbers using combinational logic

#### - RTL implementation of the conversion of binary numbers to binarycoded-decimal (BCD) encoder (binary to BCD conversion) using the "shift-add-3" algorithm

#### - RTL implementation of the a seven-segment decoder (SSD) using combinational logic.

#### - Integration of the above three blocks as shown in the figure below:



![image](https://user-images.githubusercontent.com/42722816/114174617-23ef4100-9939-11eb-8ec9-0e145db5f907.png)

Figure 1: Block diagram for the integrated multiplier



## BCD Encoder using the "shift-add-3" algorithm

#### This will be implemented using shift-add-3 algorithm.

#### Now, the question is how to implement this in your circuit.

#### First, we need a macro which has a four-bit input and four-bit output and which performs the operation "add 3 if the input is 5 or greater". This is up to you to design however you want. Then, the converter can be arranged in the following manner:



![image](https://user-images.githubusercontent.com/42722816/114174767-61ec6500-9939-11eb-9590-cbee90248459.png)



# Seven-segment Decoder (SSD)

#### 7-segment displays are paired to display numbers in various sizes. The figure below

#### shows the connection of seven segments (common anode) to pins on Cyclone V FPGA.

#### The segment can be turned on or off by applying a low logic level or high logic level

#### from the FPGA, respectively. Develop the truth table for converting BCD to the 7-

#### segment display decoder. For example, BCD=0000 will correspond to SSD=100000,BCD=0001 will correspond to SSD=1111001, etc.



![image](https://user-images.githubusercontent.com/42722816/114174918-a11ab600-9939-11eb-8d4d-2fbc5489c90e.png)





## Result ScreenShots





### Multiplier

![multiplier](https://user-images.githubusercontent.com/42722816/114238428-e2848300-9984-11eb-8983-f8c389b170ac.png)





### BCD

![bcd](https://user-images.githubusercontent.com/42722816/114238464-f203cc00-9984-11eb-9b76-a74ed7c84fcb.png)





### SSD

![ssd](https://user-images.githubusercontent.com/42722816/114238471-f334f900-9984-11eb-901f-384520c68c1c.png)





### integration

![integration](https://user-images.githubusercontent.com/42722816/114238477-f4662600-9984-11eb-859f-3b9f41f9f7be.png)





## Contributors

> Thanks goes to my teammate Islam Ahmed

    

        

            

            

            


            

                Abdallah abu sedo

            

            

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            💻

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          Islam Ahmed

        

        

        🎯

        💻

        👀