https://github.com/abdelazeem201/apb-i2s
I2S (Inter-IC Sound) interface module with APB (Advanced Peripheral Bus) interface signals. It has control logic for writing and reading data to/from a 4x32-bit FIFO and generates clock (sck), word select (ws), and serial data (sd) signals for I2S transmission.
https://github.com/abdelazeem201/apb-i2s
apb asic fpga i2s synopsys vcs verilog
Last synced: 4 months ago
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I2S (Inter-IC Sound) interface module with APB (Advanced Peripheral Bus) interface signals. It has control logic for writing and reading data to/from a 4x32-bit FIFO and generates clock (sck), word select (ws), and serial data (sd) signals for I2S transmission.
- Host: GitHub
- URL: https://github.com/abdelazeem201/apb-i2s
- Owner: abdelazeem201
- License: mit
- Created: 2024-10-08T11:19:29.000Z (over 1 year ago)
- Default Branch: main
- Last Pushed: 2024-10-24T06:48:42.000Z (over 1 year ago)
- Last Synced: 2025-04-08T11:06:01.070Z (about 1 year ago)
- Topics: apb, asic, fpga, i2s, synopsys, vcs, verilog
- Language: Verilog
- Homepage:
- Size: 72.3 KB
- Stars: 3
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: Docs/Readme.md
- License: LICENSE
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README
1.0 THE I2S BUS
====================
Inter-Integrated Circuit Sound (I²S, pronounced "eye-squared-ess"[citation needed]) is a serial interface protocol for transmitting two-channel, digital audio as pulse-code modulation (PCM) between integrated circuit (IC) components of an electronic device. An I²S bus separates clock and serial data signals, resulting in simpler receivers than those required for asynchronous communications systems that need to recover the clock from the data stream. Alternatively, I²S is spelled I2S (pronounced eye-two-ess) or IIS (pronounced eye-eye-ess). Despite a similar name, I²S is unrelated to I²C.