https://github.com/abdelazeem201/cortex-m3-designstart-eval
Cortex-M3 DesignStart Eval is intended for system Verilog design and simulation of a prototype SoC based on the Cortex-M3 processor.
https://github.com/abdelazeem201/cortex-m3-designstart-eval
arm asic cadence cortex-m3 fpga processor rtl simulation soc synopsys synthesis systemverilog verilog
Last synced: about 2 months ago
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Cortex-M3 DesignStart Eval is intended for system Verilog design and simulation of a prototype SoC based on the Cortex-M3 processor.
- Host: GitHub
- URL: https://github.com/abdelazeem201/cortex-m3-designstart-eval
- Owner: abdelazeem201
- License: mit
- Created: 2023-04-25T09:58:39.000Z (about 2 years ago)
- Default Branch: main
- Last Pushed: 2023-04-30T15:18:10.000Z (about 2 years ago)
- Last Synced: 2023-07-31T23:25:00.655Z (almost 2 years ago)
- Topics: arm, asic, cadence, cortex-m3, fpga, processor, rtl, simulation, soc, synopsys, synthesis, systemverilog, verilog
- Language: Verilog
- Homepage: https://developer.arm.com/Processors/Cortex-M3
- Size: 12.3 MB
- Stars: 2
- Watchers: 1
- Forks: 1
- Open Issues: 0