https://github.com/abdullahalshawafi/risc-processor
A simple 5-stage pipelined processor following Harvard's architecture. The processor has RISC-like ISA. There are eight 2-byte general-purpose registers, and another three special-purpose registers (Program Counter, Exception Program Counter, Stack Pointer). The memory address space is 1 MB of 16-bit width and is word addressable.
https://github.com/abdullahalshawafi/risc-processor
computer-architecture pipelined-processors processor vhdl
Last synced: 3 months ago
JSON representation
A simple 5-stage pipelined processor following Harvard's architecture. The processor has RISC-like ISA. There are eight 2-byte general-purpose registers, and another three special-purpose registers (Program Counter, Exception Program Counter, Stack Pointer). The memory address space is 1 MB of 16-bit width and is word addressable.
- Host: GitHub
- URL: https://github.com/abdullahalshawafi/risc-processor
- Owner: abdullahalshawafi
- Created: 2021-12-09T21:16:38.000Z (over 3 years ago)
- Default Branch: main
- Last Pushed: 2022-01-10T13:57:32.000Z (over 3 years ago)
- Last Synced: 2025-01-14T06:33:31.739Z (4 months ago)
- Topics: computer-architecture, pipelined-processors, processor, vhdl
- Language: VHDL
- Homepage:
- Size: 556 KB
- Stars: 5
- Watchers: 1
- Forks: 3
- Open Issues: 0