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https://github.com/abshar-shihab/the-fast-matrix-multiplication-on-fpga
This repository explores efficient matrix multiplication on FPGA hardware. Communication between the PC and FPGA is implemented through UART.
https://github.com/abshar-shihab/the-fast-matrix-multiplication-on-fpga
fpga nexus-3 pipelined uart verilog
Last synced: 6 days ago
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This repository explores efficient matrix multiplication on FPGA hardware. Communication between the PC and FPGA is implemented through UART.
- Host: GitHub
- URL: https://github.com/abshar-shihab/the-fast-matrix-multiplication-on-fpga
- Owner: Abshar-Shihab
- Created: 2024-12-03T18:11:33.000Z (3 months ago)
- Default Branch: main
- Last Pushed: 2025-01-01T12:57:24.000Z (about 2 months ago)
- Last Synced: 2025-01-01T13:36:10.304Z (about 2 months ago)
- Topics: fpga, nexus-3, pipelined, uart, verilog
- Language: Verilog
- Homepage:
- Size: 7.22 MB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
Awesome Lists containing this project
README
# The Fast Matrix Multiplication on FPGA
## Project Overview
This project explores efficient matrix multiplication on FPGA hardware, focusing on optimizing computation speed using serial, parallel, and pipelined processing methods. Communication between the PC and FPGA is implemented through UART or Ethernet.
### Team Members:
- **U.L. Mohamed Abshar Shihab**
- **Imad ud Din**
- **Kanwar M. Umar**
### Objectives
1. Establish UART communication between the PC and FPGA.
2. Implement and test 2x2 upto 10x10 matrix multiplication on the FPGA using Verilog.
3. Optimize matrix multiplication using pipelining for increased computational speed.
### Repository Structure
```
The-fast-matrix-multiplication-on-fpga/
├── 2x2 Matrix_Multiplication/
├── Uart_Testing/
├── complete-matrix-multiplication/
│ ├── 16-Bit-Transmitter/
│ │ ├── Outputs/
│ │ │ ├── 16bit-2x2.png
│ │ │ ├── 16bit-3x3.png
│ │ ├── Python Code/
│ │ │ ├── 16bit.py
│ │ ├── BaudRateGenerator.v
│ │ ├── Uart8Receiver.v
│ │ ├── Uart8Transmitter.v
│ │ ├── Uart8_Matrix.v
│ │ ├── UartStates.vh
│ │ ├── ucf.ucf
│ ├── Matrix-Multiplication-with-pipeline/
│ │ ├── Outputs/
│ │ │ ├── 3x3-p.png
│ │ │ ├── 4x4-p.png
│ │ │ ├── 5x5-p.png
│ │ │ ├── 10x10-p.png
│ │ ├── Python Code/
│ │ │ ├── upto_Ten_Time.py
│ │ ├── BaudRateGenerator.v
│ │ ├── Uart8Receiver.v
│ │ ├── Uart8Transmitter.v
│ │ ├── Uart8_pip.v
│ │ ├── UartStates.vh
│ │ ├── ucf.ucf
│ ├── Matrix_Multiplication/
│ │ ├── Outputs/
│ │ │ ├── 3x3.png
│ │ │ ├── 4x4.png
│ │ │ ├── 5x5.png
│ │ │ ├── 10x10.png
│ │ ├── Python Code/
│ │ │ ├── upto_Ten_Time.py
│ │ ├── BaudRateGenerator.v
│ │ ├── Uart8Receiver.v
│ │ ├── Uart8Transmitter.v
│ │ ├── Uart8_Matrix.v
│ │ ├── UartStates.vh
│ │ ├── ucf.ucf
├── README.md
```
## How to Run
1. Clone the repository:
```bash
git clone https://github.com/Abshar-Shihab/The-fast-matrix-multiplication-on-fpga.git
```
2. Navigate to the appropriate folder for the desired module.
3. Follow the Python script in each folder to test the corresponding functionality.
- Use `16bit.py` for 16-bit transmitter tests.
- Use `upto_Ten_Time.py` for matrix multiplication tests.
4. Analyze the output images in the `Outputs` folder to validate the results.
## Future Goals
- Explore larger matrix sizes and improve hardware utilization.
- Compare FPGA performance against CPU and GPU implementations.