https://github.com/adamhlt/litex-cva6

LiteX CVA6 - Fixed integration of the CPU into LiteX SoC generator
https://github.com/adamhlt/litex-cva6

cva6 fpga litex python verilog

Last synced: about 1 month ago
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LiteX CVA6 - Fixed integration of the CPU into LiteX SoC generator

• Host: GitHub
• URL: https://github.com/adamhlt/litex-cva6
• Owner: adamhlt
• License: gpl-3.0
• Created: 2023-02-13T20:46:56.000Z (almost 2 years ago)
• Default Branch: main
• Last Pushed: 2023-08-01T20:58:30.000Z (over 1 year ago)
• Last Synced: 2024-12-08T22:01:27.631Z (about 2 months ago)
• Topics: cva6, fpga, litex, python, verilog
• Language: C++
• Homepage:
• Size: 13.5 MB
• Stars: 4
• Watchers: 1
• Forks: 2
• Open Issues: 1

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