https://github.com/adarshpatil/dve
Improving DRAM Reliability and Performance On-Demand via Coherent Replication [ISCA 2021]
https://github.com/adarshpatil/dve
coherence dram reliability replication sockets
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Improving DRAM Reliability and Performance On-Demand via Coherent Replication [ISCA 2021]
- Host: GitHub
- URL: https://github.com/adarshpatil/dve
- Owner: adarshpatil
- Created: 2021-03-12T17:37:13.000Z (about 5 years ago)
- Default Branch: master
- Last Pushed: 2022-06-10T10:23:39.000Z (almost 4 years ago)
- Last Synced: 2024-04-24T18:55:47.591Z (about 2 years ago)
- Topics: coherence, dram, reliability, replication, sockets
- Language: Objective-C
- Homepage: https://adar.sh/dve
- Size: 174 KB
- Stars: 7
- Watchers: 2
- Forks: 1
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
Awesome Lists containing this project
README
#  Dvé: Coherent Replication Protocol
Dvé is a memory system architecture to improve the reliability and performance of DRAM main memory. This repository contains all artifacts used to experimentally evaluate Dvé [[ISCA '21 paper]](https://www.cs.utah.edu/~rajeev/pubs/isca21.pdf).
# Features of Dvé:
- Replicates memory on two different sockets of a multi socket NUMA system
- Modifies NUMA cache coherence communication by introducing replica directory to permit local replica access
(Figure shows coherence communications in (a) Baseline NUMA (b) Dvé (c) Logical View)
- Proposes two protocol families — allow-based and deny-based — to achieve Coherent Replication
- Protocol Optimizations to further improve performance
- Speculative replica access
- Coarse-grained replica directory
- Sampling based dynamic protocol
# Repository contents
1. gem5 based implementation of Coherent Replication (forked from [VANDAL/SynchroTrace-gem5](https://github.com/VANDAL/SynchroTrace-gem5))\
The repo contains implementation of the baseline, proposed protocols and a variant of Intel's Mirroring implementation.
- numa-baseline: multi-socket NUMA baseline configuration
- deny-based protocol implementation
- allow-based protocol implementation
- intel-intel-ch-replication: An extention of Intel's Address Range Partial Mirroring implementation with read requests load balanced between both channels (requests are alternated between channels)
2. Trace generator (forked from [VANDAL/prism](https://github.com/VANDAL/prism))
3. Coherence protocol [specification](https://github.com/adarshpatil/dve/blob/master/Dve-ISCA21-Appendix.pdf) in table format.
4. [Murphi model](https://github.com/adarshpatil/dve/tree/master/murphi-model) for allow-based and deny-based protocol (generated using [ProtoGen](https://github.com/icsa-caps/ProtoGen))
# Additional Material
- Full Protocol Model Checking and Verification files are available in this [github source repo](https://github.com/Errare-humanum-est/Dve_Protocol_Model_Check)
- FAQ, talk videos, slides - [https://adar.sh/dve](https://adar.sh/dve)
# Referencing our work
If you are using Dvé for your work, please cite:**
```
@inproceedings{dve-isca21,
author = {Patil, Adarsh and Nagarajan, Vijay and Balasubramonian, Rajeev and Oswald, Nicolai},
title = {Dvé: Improving DRAM Reliability and Performance On-Demand via Coherent Replication},
year = {2021},
publisher = {IEEE Press},
booktitle = {Proceedings of the ACM/IEEE 48th Annual International Symposium on Computer Architecture},
pages = {526–539},
numpages = {14},
keywords = {Memory Systems, DRAM, Reliability, Coherence},
location = {Virtual Event},
series = {ISCA '21}
}
```
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The title of the project is derived from the Sankrit word (द्वे) which means "the two",
referring here to the dual benefits of replication.