https://github.com/adolbyb/vhdl-fpga-nexys-a7

A collection of code from CDA 4240C: Design of Digital System and Lab
https://github.com/adolbyb/vhdl-fpga-nexys-a7

artix-7 fpga hardware-description-language hdl nexys-a7 verilog vhdl xilinx-vivado

Last synced: about 1 month ago
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A collection of code from CDA 4240C: Design of Digital System and Lab

• Host: GitHub
• URL: https://github.com/adolbyb/vhdl-fpga-nexys-a7
• Owner: ADolbyB
• Created: 2023-01-27T16:17:45.000Z (almost 2 years ago)
• Default Branch: main
• Last Pushed: 2023-05-26T01:48:04.000Z (over 1 year ago)
• Last Synced: 2023-05-26T03:38:56.625Z (over 1 year ago)
• Topics: artix-7, fpga, hardware-description-language, hdl, nexys-a7, verilog, vhdl, xilinx-vivado
• Language: VHDL
• Homepage:
• Size: 5.58 MB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0

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