https://github.com/adolbyb/vhdl-fpga-nexys-a7
A collection of code from CDA 4240C: Design of Digital System and Lab
https://github.com/adolbyb/vhdl-fpga-nexys-a7
artix-7 fpga hardware-description-language hdl nexys-a7 verilog vhdl xilinx-vivado
Last synced: about 2 months ago
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A collection of code from CDA 4240C: Design of Digital System and Lab
- Host: GitHub
- URL: https://github.com/adolbyb/vhdl-fpga-nexys-a7
- Owner: ADolbyB
- Created: 2023-01-27T16:17:45.000Z (over 2 years ago)
- Default Branch: main
- Last Pushed: 2023-05-26T01:48:04.000Z (over 2 years ago)
- Last Synced: 2025-03-13T23:14:06.993Z (7 months ago)
- Topics: artix-7, fpga, hardware-description-language, hdl, nexys-a7, verilog, vhdl, xilinx-vivado
- Language: VHDL
- Homepage:
- Size: 5.58 MB
- Stars: 3
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
# VHDL Code for FPGAs (With Some Verilog For Comparison)
This is a collection of code from CDA 4240C: Design of Digital Systems.
- There is a separate Verilog folder since we studied the differences between it and VHDL at the end of the course.
- My Projects were simulated and synthesized using [Xilinx Vivado 2022.2](https://www.xilinx.com/support/download.html)
- This code runs on the [Nexys A7-100T](https://digilent.com/shop/nexys-a7-fpga-trainer-board-recommended-for-ece-curriculum/) FPGA Evaluation Board:
## Status:
