https://github.com/ahmedishraq/cse460-lab

CSE460 - VLSI Design
https://github.com/ahmedishraq/cse460-lab

bracucse460 coq verilog-hdl verilog-project vhdl vlsi-design

Last synced: about 1 month ago
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CSE460 - VLSI Design

• Host: GitHub
• URL: https://github.com/ahmedishraq/cse460-lab
• Owner: ahmedishraq
• Created: 2022-10-11T09:35:35.000Z (over 2 years ago)
• Default Branch: main
• Last Pushed: 2023-02-09T20:30:19.000Z (almost 2 years ago)
• Last Synced: 2024-11-06T05:43:30.845Z (3 months ago)
• Topics: bracucse460, coq, verilog-hdl, verilog-project, vhdl, vlsi-design
• Language: HTML
• Homepage:
• Size: 5.81 MB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# CSE460 - VLSI Design

Lab solutions of CSE460 - VLSI Design course of [BRAC University,](https://www.bracu.ac.bd/) Dhaka, Bangladesh.