https://github.com/ain1084/dual_clock_buffer

Dual clock buffer for modules connected by valid-ready protocol
https://github.com/ain1084/dual_clock_buffer

protocol-buffers verilog

Last synced: about 1 month ago
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Dual clock buffer for modules connected by valid-ready protocol

• Host: GitHub
• URL: https://github.com/ain1084/dual_clock_buffer
• Owner: ain1084
• License: unlicense
• Created: 2021-01-19T12:26:43.000Z (about 4 years ago)
• Default Branch: master
• Last Pushed: 2024-11-26T13:32:54.000Z (about 2 months ago)
• Last Synced: 2024-11-26T14:31:58.325Z (about 2 months ago)
• Topics: protocol-buffers, verilog
• Language: Verilog
• Homepage:
• Size: 6.84 KB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# dual_clock_buffer

Dual clock buffer for modules connected by valid and ready handshake.

![dual_clock_buffer](https://user-images.githubusercontent.com/14823909/106747448-4c23a080-6667-11eb-8c3c-2519fdb0dc1c.png)

|Name|Direction|Clock domain|Description|

|--|--|--|--|

|reset|input|i_clk, o_clk|Reset signal (Active high)|

|i_clk|input|i_clk|Intake clock|

|i_valid|input|i_clk|Intake valid|

|i_ready|output|i_clk|Intake ready|

|i_data[width-1:0]|input|i_clk|Intake data|

|o_clk|input|o_clk|Outlet clock|

|o_valid|output|o_clk|Outlet valid|

|o_ready|input|o_clk|Outlet ready|

|o_data[width-1:0]|output|o_clk|Outlet data|