https://github.com/ain1084/serial_audio_decoder

Serial audio data (I2S or Left justified) decoder
https://github.com/ain1084/serial_audio_decoder

decoder i2s-audio verilog

Last synced: 18 days ago
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Serial audio data (I2S or Left justified) decoder

• Host: GitHub
• URL: https://github.com/ain1084/serial_audio_decoder
• Owner: ain1084
• Created: 2021-01-26T16:24:12.000Z (almost 4 years ago)
• Default Branch: main
• Last Pushed: 2024-11-26T13:32:17.000Z (about 1 month ago)
• Last Synced: 2024-11-26T14:31:47.821Z (about 1 month ago)
• Topics: decoder, i2s-audio, verilog
• Language: Verilog
• Homepage:
• Size: 10.7 KB
• Stars: 4
• Watchers: 1
• Forks: 2
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# serial_audio_decoder

Serial audio data (I2S or Left justified) decoder.Using valid-ready handshake.

![serial_audio_decoder](https://user-images.githubusercontent.com/14823909/149629735-6448fd02-b8f3-4e11-9554-f87370669edf.png)

|Name|Direction|Description|

|--|--|--|

|reset|input|reset (high active)|

|sclk|input|Serial data (sdin) clock|

|lrclk|input|Left-right clock (0 = left. See also lrclk_polarity)|

|sdin|input|Serial data|

|is_i2s|input|Serial format (0: Left justified / 1: I2S)|

|lrclk_polarity|input|Left-right clock polarity (0: low = left / 1: low = right)|

|is_error|output|error status (0: normal / 1: error)|

|o_valid|output|Output data valid signal (1: valid)|

|o_ready|input|Incoming ready signal (1: ready)|

|o_is_left|output|Channel (0: Right / 1: Left)

|o_data[audio_width-1:0]|output|Audio data (Left justified) |