https://github.com/akhilrai28/single-port-ram

This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.
https://github.com/akhilrai28/single-port-ram

digital-circuits fpga fpga-programming hardware hardware-description-language memory-design ram single-port synchronous testbench verilog

Last synced: about 2 months ago
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This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.

• Host: GitHub
• URL: https://github.com/akhilrai28/single-port-ram
• Owner: AkhilRai28
• License: mit
• Created: 2024-08-23T17:50:31.000Z (5 months ago)
• Default Branch: main
• Last Pushed: 2024-08-24T15:55:08.000Z (5 months ago)
• Last Synced: 2024-10-27T18:42:20.092Z (3 months ago)
• Topics: digital-circuits, fpga, fpga-programming, hardware, hardware-description-language, memory-design, ram, single-port, synchronous, testbench, verilog
• Language: Verilog
• Homepage:
• Size: 68.4 KB
• Stars: 3
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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# Single-Port-RAM