https://github.com/akielaries/hwverif

Sandbox for exploring Hardware Verification
https://github.com/akielaries/hwverif

verilog

Last synced: about 22 hours ago
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Sandbox for exploring Hardware Verification

• Host: GitHub
• URL: https://github.com/akielaries/hwverif
• Owner: akielaries
• Created: 2023-02-11T04:55:42.000Z (almost 2 years ago)
• Default Branch: main
• Last Pushed: 2023-12-29T08:02:47.000Z (about 1 year ago)
• Last Synced: 2023-12-29T09:23:50.442Z (about 1 year ago)
• Topics: verilog
• Language: VHDL
• Homepage:
• Size: 174 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# Exploring Hardware Verification

Another repo I use for tinkering with hardware.

# Tools

* Using **iverilog** for working with Verilog files and generating files

necessary for syntehsis.

* **NVC** & **GHDL** for doing the with VHDL. 

* **Verilator** for working with System Verilog files.

* **GTKWave** to visualize signals/running simulations. 

* **cocotb** for experimenting with test bench generation.

* **Yosys** for synthesis and generating schematics.