https://github.com/albertopirillo/logical-networks-project-2020
Implementation in VHDL of an HW component capable of recalibrating the contrast of an image stored in an external memory, using a histogram equalization algorithm.
https://github.com/albertopirillo/logical-networks-project-2020
digital-design hw vivado-hls
Last synced: 2 months ago
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Implementation in VHDL of an HW component capable of recalibrating the contrast of an image stored in an external memory, using a histogram equalization algorithm.
- Host: GitHub
- URL: https://github.com/albertopirillo/logical-networks-project-2020
- Owner: albertopirillo
- License: mit
- Created: 2021-07-24T22:29:17.000Z (almost 4 years ago)
- Default Branch: master
- Last Pushed: 2021-08-29T14:47:39.000Z (over 3 years ago)
- Last Synced: 2025-01-01T18:41:48.925Z (4 months ago)
- Topics: digital-design, hw, vivado-hls
- Language: VHDL
- Homepage:
- Size: 3.1 MB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# Prova Finale - Reti Logiche
### Engineering of Computing Systems @ Politecnico di Milano, AA. 2020-2021
The goal of the project is to use VHDL language to implement and synthesize an HW component capable of interacting with a memory to read an image, process that image using a histogram equalization algorithm and eventually write in memory the equalized image
## Resources
- Source code is available [here](sources/project_reti_logiche.vhd)
- A state diagram of the component is available [here](documentation/FSM%20Diagram.pdf)
- A detailed report is available [here](documentation/Report.pdf)
## Software
- [Xilinx Vivado Design Suite](https://www.xilinx.com/products/design-tools/vivado.html)
- [Diagrams](https://www.diagrams.net/)
- [LaTeX](https://www.latex-project.org/)
## License & Copyright
Licensed under [MIT License](LICENSE)