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https://github.com/albertopirillo/logical-networks-project-2020
Implementation in VHDL of an HW component capable of recalibrating the constrast of an image stored in an external memory, using an histogram equalization algorithm.
https://github.com/albertopirillo/logical-networks-project-2020
digital-design hw vivado-hls
Last synced: about 1 month ago
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Implementation in VHDL of an HW component capable of recalibrating the constrast of an image stored in an external memory, using an histogram equalization algorithm.
- Host: GitHub
- URL: https://github.com/albertopirillo/logical-networks-project-2020
- Owner: albertopirillo
- License: mit
- Created: 2021-07-24T22:29:17.000Z (over 3 years ago)
- Default Branch: master
- Last Pushed: 2021-08-29T14:47:39.000Z (over 3 years ago)
- Last Synced: 2023-03-05T18:39:08.876Z (almost 2 years ago)
- Topics: digital-design, hw, vivado-hls
- Language: VHDL
- Homepage:
- Size: 3.1 MB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0