https://github.com/aledpl5/rock-paper-scissors-circuit

Uni project about the game rock-paper-scissors
https://github.com/aledpl5/rock-paper-scissors-circuit

blif circuit datapath datapath-design finate-state-machine sis systemverilog verilog

Last synced: 27 days ago
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Uni project about the game rock-paper-scissors

• Host: GitHub
• URL: https://github.com/aledpl5/rock-paper-scissors-circuit
• Owner: Aledpl5
• Created: 2024-02-07T09:15:44.000Z (12 months ago)
• Default Branch: main
• Last Pushed: 2024-02-07T09:29:47.000Z (12 months ago)
• Last Synced: 2024-11-09T23:17:56.023Z (3 months ago)
• Topics: blif, circuit, datapath, datapath-design, finate-state-machine, sis, systemverilog, verilog
• Language: SystemVerilog
• Homepage:
• Size: 13.7 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# Rock-Paper-Scissors Circuit

This is a university project with the aim of designing and modeling a circuit that governs the rock-paper-scissors game.

In this repository, I use two different "modeling languages" to create the circuit:

- [SIS](https://bettersis.readthedocs.io/en/latest/tutorials/tutorials.html)

- [Verilog](https://it.wikipedia.org/wiki/Verilog)

## Collaborators

- [Mattia Danese](https://github.com/mattiadane)