https://github.com/alexforencich/verilog-cam

Verilog Content Addressable Memory Module
https://github.com/alexforencich/verilog-cam

Last synced: 8 days ago
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Verilog Content Addressable Memory Module

• Host: GitHub
• URL: https://github.com/alexforencich/verilog-cam
• Owner: alexforencich
• License: mit
• Created: 2015-11-15T09:31:23.000Z (about 9 years ago)
• Default Branch: master
• Last Pushed: 2022-03-02T08:02:06.000Z (almost 3 years ago)
• Last Synced: 2024-11-10T00:32:58.451Z (2 months ago)
• Language: Verilog
• Size: 19.5 KB
• Stars: 101
• Watchers: 12
• Forks: 48
• Open Issues: 5
• Metadata Files:
  • Readme: README
  • License: COPYING

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README

        
# Verilog CAM Readme

For more information and updates: http://alexforencich.com/wiki/en/verilog/cam/start

GitHub repository: https://github.com/alexforencich/verilog-cam

## Introduction

FPGA-independent content addressable memory module.