https://github.com/alexforencich/verilog-dsp

Verilog digital signal processing components
https://github.com/alexforencich/verilog-dsp

Last synced: 2 months ago
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Verilog digital signal processing components

• Host: GitHub
• URL: https://github.com/alexforencich/verilog-dsp
• Owner: alexforencich
• License: mit
• Created: 2015-02-17T23:20:37.000Z (almost 10 years ago)
• Default Branch: master
• Last Pushed: 2022-10-30T21:04:27.000Z (about 2 years ago)
• Last Synced: 2024-11-09T22:38:18.826Z (2 months ago)
• Language: Python
• Size: 58.6 KB
• Stars: 104
• Watchers: 7
• Forks: 37
• Open Issues: 2
• Metadata Files:
  • Readme: README
  • License: COPYING

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Verilog DSP