https://github.com/alexforencich/verilog-flowgen

Ethernet flow generator framework
https://github.com/alexforencich/verilog-flowgen

Last synced: 3 months ago
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Ethernet flow generator framework

• Host: GitHub
• URL: https://github.com/alexforencich/verilog-flowgen
• Owner: alexforencich
• License: mit
• Created: 2015-02-11T20:17:13.000Z (almost 10 years ago)
• Default Branch: master
• Last Pushed: 2015-02-25T00:04:03.000Z (almost 10 years ago)
• Last Synced: 2023-03-11T13:17:12.152Z (almost 2 years ago)
• Language: Python
• Size: 215 KB
• Stars: 6
• Watchers: 3
• Forks: 5
• Open Issues: 0
• Metadata Files:
  • Readme: README
  • License: COPYING

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README

        
# Verilog Flowgen Readme

For more information and updates: http://alexforencich.com/wiki/en/verilog/flowgen/start

GitHub repository: https://github.com/alexforencich/verilog-flowgen

## Introduction

Ethernet flow generator framework.  Includes full MyHDL testbench with

intelligent bus cosimulation endpoints.