https://github.com/alexforencich/verilog-ft245

Verilog FT245 to AXI stream interface
https://github.com/alexforencich/verilog-ft245

Last synced: 2 months ago
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Verilog FT245 to AXI stream interface

• Host: GitHub
• URL: https://github.com/alexforencich/verilog-ft245
• Owner: alexforencich
• License: mit
• Created: 2016-10-08T21:01:33.000Z (over 8 years ago)
• Default Branch: master
• Last Pushed: 2018-06-20T19:48:06.000Z (over 6 years ago)
• Last Synced: 2024-11-09T22:38:18.227Z (2 months ago)
• Language: Python
• Size: 10.7 KB
• Stars: 26
• Watchers: 4
• Forks: 13
• Open Issues: 1
• Metadata Files:
  • Readme: README
  • License: COPYING
  • Authors: AUTHORS

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README

        
# Verilog FT245 Readme

For more information and updates: http://alexforencich.com/wiki/en/verilog/ft245/start

GitHub repository: https://github.com/alexforencich/verilog-ft245

## Introduction

This is a basic FTDI FT245 USB FIFO to AXI Stream IP core, written in Verilog

with MyHDL testbenches.

## Documentation

The main code for the core exists in the rtl subdirectory.  axis_ft245.v

contains the entire implementation.  

### Source Files

    axis_ft245.v           : FTDI FT245 to AXI stream bridge

### AXI Stream Interface Example

two byte transfer with sink pause after each byte

              __    __    __    __    __    __    __    __    __

    clk    __/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__

                    _____ _________________

    tdata  XXXXXXXXX_D0__X_D1______________XXXXXXXXXXXXXXXXXXXXXXXX

                    _______________________

    tvalid ________/                       \_______________________

           ______________             _____             ___________

    tready               \___________/     \___________/

## Testing

Running the included testbenches requires MyHDL and Icarus Verilog.  Make sure

that myhdl.vpi is installed properly for cosimulation to work correctly.  The

testbenches can be run with a Python test runner like nose or py.test, or the

individual test scripts can be run with python directly.

### Testbench Files

    tb/axis_ep.py        : MyHDL AXI Stream endpoints

    tb/ft245.py          : MyHDL FT245 model