https://github.com/alexforencich/verilog-lfsr

Fully parametrizable combinatorial parallel LFSR/CRC module
https://github.com/alexforencich/verilog-lfsr

Last synced: 15 days ago
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Fully parametrizable combinatorial parallel LFSR/CRC module

• Host: GitHub
• URL: https://github.com/alexforencich/verilog-lfsr
• Owner: alexforencich
• License: mit
• Created: 2016-03-31T22:56:07.000Z (about 9 years ago)
• Default Branch: master
• Last Pushed: 2025-02-27T23:53:33.000Z (about 2 months ago)
• Last Synced: 2025-03-28T21:01:56.263Z (22 days ago)
• Language: Python
• Homepage:
• Size: 65.4 KB
• Stars: 146
• Watchers: 12
• Forks: 57
• Open Issues: 2
• Metadata Files:
  • Readme: README
  • License: COPYING

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README