https://github.com/alexforencich/verilog-wishbone

Verilog wishbone components
https://github.com/alexforencich/verilog-wishbone

Last synced: 10 days ago
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Verilog wishbone components

• Host: GitHub
• URL: https://github.com/alexforencich/verilog-wishbone
• Owner: alexforencich
• License: mit
• Created: 2013-11-24T08:15:54.000Z (over 11 years ago)
• Default Branch: master
• Last Pushed: 2024-01-05T13:55:22.000Z (over 1 year ago)
• Last Synced: 2025-04-10T03:16:38.888Z (10 days ago)
• Language: Python
• Size: 163 KB
• Stars: 114
• Watchers: 15
• Forks: 31
• Open Issues: 5
• Metadata Files:
  • Readme: README
  • License: COPYING
  • Authors: AUTHORS

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• awesome-opensource-hardware - verilog-wishbone

README