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https://github.com/alexfru/regal86

8086 assembly code-generation compiler compiler-backend compiler-design compiler-optimization dos expression-evaluation register-allocation x86

Last synced: 4 days ago
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Host: GitHub
URL: https://github.com/alexfru/regal86
Owner: alexfru
License: bsd-2-clause
Created: 2021-04-27T06:23:45.000Z (over 3 years ago)
Default Branch: master
Last Pushed: 2023-08-20T23:36:43.000Z (about 1 year ago)
Last Synced: 2023-08-21T00:23:52.029Z (about 1 year ago)
Topics: 8086, assembly, code-generation, compiler, compiler-backend, compiler-design, compiler-optimization, dos, expression-evaluation, register-allocation, x86
Language: Assembly
Homepage:
Size: 55.7 KB
Stars: 70
Watchers: 4
Forks: 6
Open Issues: 0
Metadata Files:
- Readme: readme.md
- License: LICENSE

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README

# Local Register Allocator for 8086

## Table of contents

[What is this?](#what-is-this)

[Motivation](#motivation)

[Scope](#scope)

[Basic algorithm](#basic-algorithm)

[8086-specific approach](#8086-specific-approach)

[Resources](#resources)

## What is this?

This is an implementation of a greedy bottom-up local register allocator for
the intel 8086 CPU. It may be used as part of a simple compiler. In particular,
it can be used in a C compiler whose `int` is 16-bit and `char` is 8-bit.

To make things interesting and interactive it comes with a code generator
capable of generating 8086 assembly code (compilable into DOS .COM programs)
from trees representing expressions with 16-bit integer ALU operations,
constants and memory loads and stores. A few extra instructions generated by
the code check the results of expression evaluation in the output register and
the output memory locations, if any.

Thus you can actually execute the generated code and tweak things around to see
how your changes affect code generation.

Sample assembly output from the register allocator/code generator:

; 7 (vr4)
; mul (vr5)
; 5 (vr3)
; add (vr6)
; 3 (vr1)
; mul (vr2)
; 2 (vr0)
; ----
; Regs needed (approximately): 3
; --------
; ; vr0
mov ax, 2 ; vr0
mov cx, 3 ; vr1
mul cx ; vr2
mov cx, 5 ; vr3
mov dx, 7 ; vr4
xchg ax, cx ; vr5
mul dx ; vr5
add cx, ax ; vr6
; ; vr6
cmp cx, 41 ; vr6
jne failure ; vr6

N.B. This register allocator will not allocate registers perfectly in all
circumstances. It will occasionally generate unnecessary register moves and
exchanges. Bear in mind, optimal register allocation is an NP-complete problem.

## Motivation

The intel 8086 architecture has a number of instructions with fixed input
and/or output registers and it's not entirely trivial to connect the ins and
outs of these instructions. There's obviously a long history of implementing
compilers for this and similar architectures, but it's a bit odd that it's
hard to find a conceptually simple algorithm like this. The "Dragon" book and
many other sources either consider architectures without instructions with such
fixed register operands or solve the problem using graph coloring, which for
certain reasons may be impractical.

The intel 8086 architecture survives to this day in the modern intel Pentium
CPUs that are compatible descendants of the old 8086 and with it survive some
of the instructions with fixed in/out register operands. So, the problem
persists to this day, although there are fewer limitations to deal with when
using newer 32-bit and 64-bit x86 instructions and registers today.

8086 registers by special uses in expression evaluation (pardon the mixture of
C and assembly operators, instructions and syntax and ASCII art):