https://github.com/algosup/2024-2025-project-1-fpga-team-5

1st project of the year 2024-2025, recreate Frogger in FPGA / verilog
https://github.com/algosup/2024-2025-project-1-fpga-team-5

fpga retrogaming school-project verilog

Last synced: about 6 hours ago
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1st project of the year 2024-2025, recreate Frogger in FPGA / verilog

• Host: GitHub
• URL: https://github.com/algosup/2024-2025-project-1-fpga-team-5
• Owner: algosup
• License: mit
• Created: 2024-09-23T12:55:45.000Z (about 2 months ago)
• Default Branch: main
• Last Pushed: 2024-10-28T19:37:21.000Z (19 days ago)
• Last Synced: 2024-11-13T19:11:54.637Z (3 days ago)
• Topics: fpga, retrogaming, school-project, verilog
• Language: Verilog
• Homepage:
• Size: 3.56 MB
• Stars: 5
• Watchers: 0
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE
  • Code of conduct: CODE_OF_CONDUCT.md

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README

        
# 2024 2025 - Project 1 FPGA - Team 5

## Project Description

For the first project of the new scholar year, ALGOSUP asked us to recreate the video game [Frogger](https://en.wikipedia.org/wiki/Frogger).

The game is a simple arcade game where the player has to move a frog from the bottom of the screen to the top while avoiding obstacles such as cars and water. The player can move the frog in four directions: up, down, left and right. The frog has to avoid the obstacles and reach the top of the screen to win the game.

The language used for this project is Verilog, an easy-to-understand hardware description language. The game will be displayed on a VGA screen, which is a common screen used in computer hardware.

## Team Members

| Name              | Role              | Picture                                                                                                                 | Link to LinkedIn                                                              |

| ----------------- | ----------------- | ----------------------------------------------------------------------------------------------------------------------- | ----------------------------------------------------------------------------- |

| Alexis Lasselin   | Project Manager   |    | [Alexis Lasselin](https://www.linkedin.com/in/alexis-lasselin-318649251/)     |

| Rémy Charles      | Program Manager   |       | [Rémy Charles](https://www.linkedin.com/in/r%C3%A9my-charles-2a8960232/)      |

| Michel Riff       | Tech Lead         |         | [Michel Riff](https://www.linkedin.com/in/michel-riff-693007293/)             |

| Mathias Gagnepain | Software Engineer |  | [Mathias Gagnepain](https://www.linkedin.com/in/mathias-gagnepain/)           |

| Camille Gayat     | Quality Assurance |      | [Camille Gayat](https://www.linkedin.com/in/camille-g-a89114293/)             |

| Salaheddine Namir | Technical Writer  |             | [Salaheddine Namir](https://www.linkedin.com/in/salaheddine-namir-3402471b8/) |

## Documents links

- [Functional Specification](./Documents/Specification/Functional/FunctionalSpecification.md)

- [Technical Specification](./Documents/Specification/Technical/TechnicalSpecification.md)

- [Test Plan](./Documents/TestPlan/TestPlan.md)

- [User Manual](./Documents/UserManual/UserManual.pdf)

- [Weekly Reports](./Documents/Management/WeeklyReports/)

- [Management Artifacts](./Documents/Management/ManagementArtifacts.md)