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https://github.com/ali-ahmadii/verilog_intro
Simple Verilog Projects
https://github.com/ali-ahmadii/verilog_intro
Last synced: 9 days ago
JSON representation
Simple Verilog Projects
- Host: GitHub
- URL: https://github.com/ali-ahmadii/verilog_intro
- Owner: Ali-Ahmadii
- Created: 2022-08-25T08:08:07.000Z (about 2 years ago)
- Default Branch: main
- Last Pushed: 2022-10-09T17:30:37.000Z (about 2 years ago)
- Last Synced: 2023-06-28T10:21:07.393Z (over 1 year ago)
- Language: Verilog
- Size: 5.86 KB
- Stars: 1
- Watchers: 1
- Forks: 0
- Open Issues: 0