https://github.com/amanley97/23rv-core

Just a couple of nerds making a RISC-V Softcore
https://github.com/amanley97/23rv-core

risc-v softcore systemverilog

Last synced: about 1 year ago
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Just a couple of nerds making a RISC-V Softcore

• Host: GitHub
• URL: https://github.com/amanley97/23rv-core
• Owner: amanley97
• License: mit
• Created: 2025-03-05T22:53:21.000Z (over 1 year ago)
• Default Branch: main
• Last Pushed: 2025-03-06T01:50:22.000Z (over 1 year ago)
• Last Synced: 2025-03-06T02:36:44.029Z (over 1 year ago)
• Topics: risc-v, softcore, systemverilog
• Language: Python
• Homepage:
• Size: 1000 Bytes
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

          
# 23RV-core

Just a couple of nerds making a RISC-V Softcore