https://github.com/amey-thakur/digital-logic-design-and-analysis-and-digital-system-lab
CSC302: Digital Logic Design and Analysis [DLDA] & CSL301: Digital System Lab [DS Lab] <Semester III>
https://github.com/amey-thakur/digital-logic-design-and-analysis-and-digital-system-lab
amey ameythakur computer-engineering computer-science digital-logic-design digital-logic-design-lab digital-system-design digital-systems digital-systems-design engineering megasatish textbooks
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CSC302: Digital Logic Design and Analysis [DLDA] & CSL301: Digital System Lab [DS Lab] <Semester III>
- Host: GitHub
- URL: https://github.com/amey-thakur/digital-logic-design-and-analysis-and-digital-system-lab
- Owner: Amey-Thakur
- Created: 2022-02-06T13:34:36.000Z (over 3 years ago)
- Default Branch: main
- Last Pushed: 2024-03-13T15:46:14.000Z (over 1 year ago)
- Last Synced: 2025-01-25T15:17:55.780Z (5 months ago)
- Topics: amey, ameythakur, computer-engineering, computer-science, digital-logic-design, digital-logic-design-lab, digital-system-design, digital-systems, digital-systems-design, engineering, megasatish, textbooks
- Homepage: https://github.com/Amey-Thakur/COMPUTER-ENGINEERING
- Size: 185 MB
- Stars: 10
- Watchers: 2
- Forks: 1
- Open Issues: 0
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Metadata Files:
- Readme: README.md