https://github.com/amir78729/logical-circuits-course-final-project

My Logical Circuits course Final Project - Fall98(2019) - VERILOG
https://github.com/amir78729/logical-circuits-course-final-project

logical-circuits verilog

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My Logical Circuits course Final Project - Fall98(2019) - VERILOG

• Host: GitHub
• URL: https://github.com/amir78729/logical-circuits-course-final-project
• Owner: amir78729
• Created: 2020-01-28T23:49:15.000Z (about 5 years ago)
• Default Branch: master
• Last Pushed: 2020-09-05T17:55:46.000Z (over 4 years ago)
• Last Synced: 2024-11-17T14:56:17.107Z (3 months ago)
• Topics: logical-circuits, verilog
• Language: Verilog
• Homepage:
• Size: 3.52 MB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# Logical Circuits course - final project 💻

>Computer Eng. Dept., Amirkabir University of Tech.

### 👥Collaborators

- [Negin Hajisobhani](https://github.com/neginhsobhani)

- [Amirhossein Alibakhshi](https://github.com/amir78729)

### 📝Assignments

- [click here!](https://github.com/amir78729/Logical-Circuits-Course-Final-Project/blob/master/phase1/LogicDesignProjectFirstPhase.pdf)