https://github.com/anjanasenanayake/verilog-model-for-4bit-alu

4 bit ALU in verilog
https://github.com/anjanasenanayake/verilog-model-for-4bit-alu

4bit alu computer-architecture fulladder latch verilog verilog-hdl

Last synced: 5 days ago
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4 bit ALU in verilog

• Host: GitHub
• URL: https://github.com/anjanasenanayake/verilog-model-for-4bit-alu
• Owner: AnjanaSenanayake
• Created: 2017-09-09T10:30:12.000Z (about 8 years ago)
• Default Branch: master
• Last Pushed: 2017-09-09T10:34:37.000Z (about 8 years ago)
• Last Synced: 2025-02-28T21:12:58.544Z (7 months ago)
• Topics: 4bit, alu, computer-architecture, fulladder, latch, verilog, verilog-hdl
• Language: Verilog
• Size: 1.95 KB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

          
# ALU

4 bit ALU in verilog