https://github.com/anupam-io/es203-coa-cnn

ES-203 Computer Organization & Architecture CNN on FPGA board
https://github.com/anupam-io/es203-coa-cnn

cnn cnn-classification cnn-keras cnn-model fpga fpga-programming machine-learning machinelearning verilog vivado

Last synced: 15 days ago
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ES-203 Computer Organization & Architecture CNN on FPGA board

• Host: GitHub
• URL: https://github.com/anupam-io/es203-coa-cnn
• Owner: anupam-io
• Created: 2021-03-23T13:22:16.000Z (almost 4 years ago)
• Default Branch: main
• Last Pushed: 2022-02-23T09:04:33.000Z (almost 3 years ago)
• Last Synced: 2024-10-28T17:27:30.442Z (2 months ago)
• Topics: cnn, cnn-classification, cnn-keras, cnn-model, fpga, fpga-programming, machine-learning, machinelearning, verilog, vivado
• Language: Verilog
• Homepage:
• Size: 16.1 MB
• Stars: 8
• Watchers: 1
• Forks: 8
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# ES-203 Computer Oraganization & Architecture CNN on FPGA board

## Overview









## Video Demostration

 - [Computer Organization & Architecture CNN Machine learning project on FPGA board | ES 203 Project](https://youtu.be/3J2X-j0z2M8)

## Vivado files

 - [Main Verilog CNN file](https://github.com/akcgjc007/ES203-COA-CNN/blob/main/Vivado%20CNN/CNN.srcs/sources_1/new/CNN.v)

## Tips for LUT Optimization

Here, I am mentionaing some methods for converting your C type `for-loops` into efficient `always` blocks with chaining one to another

### 1: How to convert a for loop into verilog always block

```

// C code

for(int i = 0; i Same process implemented using always a block & a flag

```

integer i = 0, flag = 0;

...code

{ flag = 1; }	// when required

always@(posedge clock)

if(flag)

begin

		if(i==n) flag = 0;

		else

	begin

		operations and functions

		i = i+1;

	end

end

```

### 2: How to convert Nested for-looping into verilog always block

```

// C code

for(int i = 0; i Same process implemented using always a block & a flag

```

integer i, j, flag;

{ flag = 1; }	// when required

always@(posedge clock)

if(flag)

begin

 if(i == 0 && j == 0)

	begin

 	Outer Loop initialization statements

		operations and functions;

	end

	else if( i == m )

	begin

		flag = 0;	// process completed

	end

	else if( j == n )

	begin 

		j = 0;	// intitialization statements analogous to inner for-loop 

		i = i+1; // updation statement of outer for loop

		operations and functions;

	end

	else

	begin

		operations and functions;

		j = j+1;

	end

end

```

## Outputs on FPGA board



## Presentation poster



## Contributors

  

    

      

          

          


          Lovepreet Singh

      

        

    

      

          

          


          Anupam Kumar

      

    

	

      

          

          


          Jayesh Salunkhe

      

    

    

      

          

          


          Unnat Dave

      

    

    

      

          

          


          Bhavesh Solanki